1. Field of the Invention
This invention generally relates to a semiconductor device and particularly to a programmable logic array (PLA) or programmable array logic (PAL) having a fixed logic circuit as a part. More specifically, the present invention relates to a reprogrammable or erasable PLA or PAL including a plurality of reprogrammable, non-volatile semiconductor memory elements, such as floating avalanche injection metal oxide semiconductors (FAMOSs) and metal silicon nitride oxide semiconductors (MNOSs).
2. Description of the Prior Art
A typical prior art PLA includes permanently programmable memory elements, such as fusible links and PN junctions, which are permanently programmed by selective thermal destruction. Typically, the bipolar process is used to manufacture prior art PLAs, and, thus, although the prior art PLAs are relatively fast in operation, they suffer from such disadvantages as low density, large power consumption and inability for reprogramming.
Under the circumstances, the present inventor previously proposed a PLA employing reprogrammable, non-volatile semiconductor memory elements as disclosed in U.S. Pat. No. 4,503,520, issued Mar. 5, 1985, and schematically illustrated in FIG. 1. That is, as shown in FIG. 1, the proposed PLA includes a NOR gate comprised by arranging a plurality of FAMOSs 1-1 through 1-n in the form of an array, and programming is carried out by having electrons injected into the floating gates of selected ones of FAMOSs. With this NOR gate as a basic unit, a combinational logic circuit having a desired function may be constructed. In such a PLA, during operation, current in the order of 1 mA flows in a sense circuit 2. This level of current must be maintained even if the sense circuit 2 is optimally designed. Moreover, approximately 36-72 of such a sense circuit 2 are required to be provided in a typical PLA or PAL and thus the level of current ranges between 36 and 72 mA, which is relatively large.